NSTC Part 2 — Fortune Favors the Bold!
Investment, IP, geography, and juicy takes on bureaucratic organization
The National Semiconductor Technology Center (NSTC) has been slower to materialize than manufacturing grants funding under the CHIPS and Science Act of 2022, but this public-private consortium with $11 billion in federal funding behind it has even more potential upside than the $39 billion of manufacturing subsidies.
In a deep-dive report published at the Institute for Progress, Chip Capitols and I highlight market failures that challenge research and investment in the semiconductor industry and propose an organizational infrastructure that would allow the NSTC to plug these holes as a unique market actor.
To maximize its potential impact, the NSTC needs to shoot for the moon.
It should make high variance bets that could really move the needle on US technological leadership for this century, not just supplement corporate R&D roadmaps.
Be sure to check out the Institute for Progress for the full report!
On weds I ran part 1. Today we getting into part 2 that explores investment, IP, geography, and bureaucratic organization.
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Correcting market failures in investment
Congress provided limited instruction regarding how the NSTC’s investment fund should function, and the Commerce Department’s 2023 “A Vision and Strategy for the NSTC” document does not specify what particular financing mechanisms the consortium plans to leverage. U.S. Code simply states that a function of the NSTC shall be:
“to establish and capitalize an investment fund, in partnership with the private sector, to support startups and collaborations between startups, academia, established companies, and new ventures, with the goal of commercializing innovations that contribute to the domestic semiconductor ecosystem, including
(i) advanced metrology and characterization for manufacturing of microchips using 3 nanometer transistor processes or more advanced processes; and
(ii) metrology for security and supply chain verification.”
Although the NSTC’s empowering legislation enumerates the two responsibilities above, the law does not limit the consortium to only metrology-related tasks. NSTC leadership can act across industry segments, and it should use this flexibility to align its investment agenda with its research agenda. Such alignment would form a powerful signal to capital providers that semiconductor startups are ripe for funding.
Investment signaling from a well-funded and technically competent institution like the NSTC would greatly benefit the chip industry. Venture capital firms like a16z, as well as larger institutional investors, generally do not have staff with deep experience in the chip industry, making them unlikely to lead funding rounds for startups whose markets they do not understand. In contrast, NIST regularly publishes roadmaps for even niches of the chip industry like die-level failure analysis, but investors lament that NIST’s signals are weak without the government also putting financial skin in the game.
The NSTC’s investment arm will not have perfect insight into the industry, but a clear research agenda can help it evangelize a clear investment agenda. In-Q-Tel stands as an extreme case study. It is the U.S. intelligence community’s sole investment arm, so third-party investors analyze its funding decisions as the key signal to what technologies a major government customer cares about. The U.S. government has not been a large enough customer to set the semiconductor industry’s agenda since the mid-20th century, but an investment agenda well aligned with the NSTC’s research agenda can give the government a meaningful role in assembling industry stakeholders and setting long-term moonshots.
Bridging the “valley of death”
The NSTC should focus investment on Series A and Series B startups to help these firms think about commercialization, not just survival. As part of their focus on surviving through seed and Series A, chip startups use equipment not used under commercial conditions, and often accept short-term deals from EDA providers like Cadence and Synopsys. These deals generously subsidize tool use until Series A, but once a startup raises a threshold amount of funds, EDA license payments suddenly trigger. Some startups simply cannot afford to raise their Series A as a result of these license triggers, leaving their products far from ever being commercialized.
Though the chip industry has grown from receiving only the 25th most venture funding in 2018 to the 11th most in 2023, chip startups still lack strategic investors with both large funds and deep technical insight. The top semiconductor seed investors come from either generalist funds which lack expertise, or chip firms’ in-house funds, which adhere to existing industry research agendas. Silicon Catalyst is the world’s only incubator focused solely on developing ambitious semiconductor solutions. Though it does great work, our interviewees repeatedly bemoaned that its limited resources and administrative structure force Silicon Catalyst, with an annual revenue of just $2M, to be selective to the point of excluding many promising upstarts.
Though such selectivity from strategic investors is commonplace across industries, it risks allowing otherwise worthy chip startups to look abroad for less conservative sources of funding. In a representative 2022 month, 58 Chinese startups seeking venture funding were successful, raising $1.27 billion, 56.27% of that month’s global chip startup funding. In contrast, only 17 U.S. startups successfully raised money that month, raising $710 million or 31.26% of the global total. Though these statistics cannot predict the relative success rate of either country’s startups, a well-funded, technically informed institution like the NSTC could help the U.S. catch up to China in the number of entrepreneurs it could help bridge the valley of death.
By leveraging the U.S. government’s and industry participants’ technical expertise alongside its significant funding, the NSTC can offer startups the advisory support and subsidized EDA licenses that only a small share of worthy entrepreneurs currently enjoy. As the chip world’s newest investor and incubator, the NSTC could help semiconductor startups survive the valley of death dividing prototyping and commercialization.
Building on- and off-ramps for underdogs
To avoid duplicating efforts by foreign consortia and to fill gaps left by the private sector, the NSTC should avoid chip industry segments that are overly saturated. Due to their lower capital cost, chip design startups receive the lion’s share of venture capital (VC) funding for the semiconductor industry. Of the 1343 global (including China) chip startups receiving VC funding tracked by one study, over half – 750 – were design startups. Although that study could not accurately capture the breakdown in funding each sector received, 18 of the 25 startups receiving the most funds engage in design activity. This relative abundance of design funding is partially due to the explosive growth in AI-related chip design. Design startups targeting AI use-cases received $6.5 billion of the $14.4 billion in raised capital held by private chip companies outside China as of July 2023 according to Pitchbook.
Instead of focusing on areas that are already receiving major private sector investment, the NSTC should support technology breakthroughs in fields that operate more like public goods, often where high capital and infrastructure barriers discourage individual companies from taking a lead. For instance, it could consider alternatives to PFAS chemicals, or solutions to deeply engrained vulnerabilities in heterogeneously integrated chips. Some research into on-chip governance mechanisms could also be appropriate, especially when these tools need to cohere with software and IP designed by different firms for the same chip. The pay-offs of such research strains may come in the form of preventing chemical run-off, enhanced national security, and assured Large Language Model (LLM) end-user privacy. In other words, the NSTC should leverage its ability to advance high-leverage technologies whose costs and pay-off may not be neatly internalized by the firms which are typically making investment decisions.
Leading rounds as a strategic investor
As the traditional free-market paradigm goes, the private sector can allocate capital more efficiently than the government. However, this aphorism misses how semiconductor companies with venture capital arms actually organize investment rounds. Different firms in different parts of the industry will have unique insight into limited sets of technology verticals, and the NSTC’s investment fund could serve to organize funding syndicates as an external moderator.
For example, Intel may know precisely what future equipment could serve its processes well, but it may not know what software design tools Qualcomm would find valuable. Furthermore, neither company’s venture arm will necessarily be focused on risky, potentially paradigm-shifting technologies, for the simple reason that such efforts could either fail or successfully upend their existing business models. At $2.2 billion in funding, SRC comes close to the sort of technically informed investment organizer the NSTC ought to become. However, SRC’s research and investment agenda, the previously mentioned Decadal Plan, largely focuses on existing industry niches. To fill a gap not yet filled by in-house venture funds and SRC, the NSTC’s venture arm should think about semiconductor breakthroughs needed by downstream technologies, like machine learning, heterogeneous integration, and sustainability.
Successfully orchestrating funding syndicates will often require the NSTC to take a leading position. The amount it would need to invest to lead on a given round depends on the stage of the startup, but private entities leading chip startup rounds usually put up between $10 million to $20 million. In contrast, non-leading participants usually only contribute $5 million. The large amounts are themselves testament to the capital barriers semiconductor startups face. For example, a startup based in the U.S. with 50 employees could face an initial annual burn rate of $10 million, rapidly growing to $30 million and $40 million as the startup’s IP license dues grow. Due to these rising operational costs, in each successive round, the size of the anchor investment would need to keep pace with the total round size.
Different niches for different consortia
Though the NSTC should be the broadest chip industry gathering place in a generation, existing semiconductor public-private partnerships around the world offer valuable case studies on how research consortia gather different players in pursuit of overlapping research goals. The legal and financial building blocks we describe in the next section for the NSTC derive from these consortia’s operational models.
Foreign consortia generally fall under two categories: those focusing on “More Moore,” continuing node size shrinkage in line with Moore’s Law, and those pursuing “More than Moore.” Most institutions do not fit neatly in one category or another, and the NSTC’s research agenda will feature characteristics of both.
As examples of “More Moore,” Belgium’s Imec and Taiwan’s ITRI have long pushed the boundaries of semiconductor manufacturing equipment and process technology. Because generational advancements in node size are such major efforts, the role of startups in these consortia’s flagship research projects is limited. The NSTC will have to consider whether its “More Moore” goals have too fixed a trajectory for smaller players to play meaningful roles.
Imec
The Interuniversity Microelectronics Center (Imec) secured its spot in industry history books for its role in developing extreme ultraviolet (EUV) lithography tools, and it continues to work closely with industry players to push the boundaries of semiconductor lithography, deposition, and etching equipment. The center offers researchers across the industry access to facilities for developing new, full-stack, CMOS (the primary fabrication process for memory, logic, and analog chips) paradigms through its system-technology co-optimization (STCO) sandbox. In addition to pushing the boundaries on CMOS paradigms, Imec’s facilities also offer pilot wafer runs for narrower innovations by startups in sensors and telecommunications for specific industry applications.
ITRI
On the other side of the planet, Taiwan’s Industrial Technology Research Institute (ITRI) similarly supports companies trying to push the boundaries of Moore’s Law, as well as those trying to get around it. Programs to develop advanced metrology tools and techniques support firms like TSMC seeking to manufacture chips with ever-smaller node sizes. Like Imec, however, ITRI also supports logic and memory chipmakers’ “More than Moore” efforts to increase the efficiency of existing node-generations through heterogeneous integration.
By contrast, the “More than Moore” consortia are often located in regions without advanced-node semiconductor manufacturing or design capabilities. Seeking to support the strengths of local chipmakers and downstream clients, they instead focus on increasing the efficiency and applicability of legacy-node chips. Because these consortia seek new applications within existing technology generations, they tend to aggressively search out and support local startups.
Leti
France’s Leti (Laboratoire d’électronique des technologies de l’information) serves to reduce the risk of developing new chip technologies for industrial applications by outsourcing applied research for industrial partners. It works with legacy chipmakers like STMicroelectronics and GlobalFoundries to develop more energy efficient materials and architectures for sensors, telecommunications, power electronics, and optics. Its related investment arm, CEA Investissement, also searches out startups in these fields to develop the consortium’s patent portfolio for industrial applications. These semiconductor innovations then feed into the mostly European original equipment manufacturer (OEM) customers that buy from Leti’s upstream chipmaking partners.
A*Star
Singapore’s Agency for Science Technology and Research (A*Star) operates the country’s Institute of Microelectronics (IME), which focuses its research on advanced packaging, MEMS, SiC, mmWave GaN, and photonics and sensors. On the advanced packaging side, IME offers a heterogeneous integration pilot line for companies to integrate different chiplets, boasting approaches for both dissimilar technologies and dissimilar wafer materials. The institute conducts both self-initiated research and research partnerships focused on applying silicon carbide to power electronics (wide-bandgap semiconductors). On the optics and sensors side, it conducts R&D prototyping and small scale manufacturing for micro electrical multi-physical systems (MEMS) that serve medical device applications. A*Star IME’s technical niches overlap with those of Leti, leading some of Leti’s key French partner firms like Soitec to also collaborate with the Singaporean institute.
Bureaucratic building blocks
Companies and universities participate in research consortia to access intellectual property that they are not capable of developing alone. They may be willing to contribute technology they have already developed in the form of “background IP,” to help consortium partners conduct joint research into breakthroughs shared with all participants in the form of “foreground IP.” This legal instrument is the lynchpin of any research consortium’s operational model and long-term financial sustainability.
Semiconductor consortia historically take a range of approaches to sharing IP with their partners, from making all findings public to exclusively licensing findings to commercial customers. These IP sharing models should pair with the structural features of the consortium. For example, a consortium receiving a large share of its funding from member companies cannot share its IP as widely as a primarily publicly funded consortium could. America’s last major semiconductor research consortium, SEMATECH, infamously failed when member companies stopped paying contributions due to an IP policy change. The consortium decided to drop its two-year moratorium during which only member companies could license consortium IP, and this caused fee-paying members to feel shortchanged. In other words, the heavily private-sector funded consortium adopted a policy befitting a primarily publicly funded consortium.
This section identifies approaches leaders in Natcast could take to ensure the NSTC’s IP sharing model coheres with its level of subsidization, membership, and research agenda. If these factors are not internally consistent, the consortium may become financially unsustainable after only five years.
Picking the right IP model
Policymakers must pick IP models that facilitate commercialization of the NSTC’s research, but some IP policies will simply not be compatible with the NSTC’s membership and research output. Critically, if the center does not receive enough funding from the government, it may need to leverage IP tools to siphon revenue to itself.
A 2021 paper by the Institute for Defense Analyses lays out the four most prominent IP models for PPPs. The NSTC’s IP sharing model should progress down this spectrum from a combination of models #1 and #2 in its initial five years, toward models #3 and #4 after a decade.
Open Access: At the least restrictive end of the spectrum, consortia could make all IP open to the public by publishing results and not requiring licensing fees to implement findings. These are most common for PPPs focused on basic research.
Shared, Limited to Partners Only: Here, members have free access to any IP developed by the PPP through nonexclusive royalty-free licenses. Use may be limited, though, to “evaluative work” that does not solely benefit an individual firm’s priorities.
Shared, Limited to R&D Collaborators: At the tightest end of the sharing spectrum, only members who participated in a specific technology’s development own the resulting IP. Access for other consortium members varies.
Exclusive Model: Some consortia license technology on an exclusive basis to third parties. These tend to occur in PPPs focusing on late-stage research, and such licenses are a significant source of income for those consortia.
In addition to differing between each other in their IP sharing models, many consortia change their models over time. NSTC leaders will have to dynamically adjust their IP model as the answers to the following questions about the consortium change:
Does the consortium receive a large or small share of its funding from the government? Does it have a homogenous or diverse membership? Does it focus on one stage of technological development or research the full stack? These factors all require different allocations of IP rights.
Levels of federal subsidization
Consortia receiving a relatively large share of their annual budget from governments have much more flexibility to share their IP among members and the public, pushing them toward the public/open access camp. In contrast, consortia receiving a relatively small share of their funding from governments either have to own their IP for the associated royalty revenue or alternatively rely on membership fees.
If a consortium decides to own its IP, then it is likely to rely on the exclusive model of licensing IP to third parties. Meanwhile, relying heavily on membership fees obliges a consortium to share limited IP rights to its members only, as these companies would be loath to see outsiders free ride on their contributions.
As we elaborate in the next section, Natcast should follow Imec’s financial model, allowing government funding from the CHIPS Act to form the majority of the NSTC’s funding in its first five years. Such a financial plan will allow the NSTC to share its IP as a public good in its earlier years, allowing small startups, universities, and large firms to equally benefit from the consortium’s foundational research.
Homogenous vs. diverse membership
Four types of stakeholders often join research consortia: start-ups, big industry, academia, and government. Each has different contributions to make to the consortium, as well as different needs regarding IP. Critically, the more diverse a consortium’s membership is, the more flexible it will need to be in its IP policy.
Start-ups often have the least to contribute to consortia, but the greatest ability to leverage a PPP to benefit society at large. Since most of a start-up’s value is based on its IP, founders are naturally hesitant to share their background IP with other coalition members. Any leakage of core IP to well-established competitors could jeopardize their chances of receiving the next round of funding. Nonetheless, if consortia accommodate start-ups by requiring less background IP sharing from them, these small players can leverage the consortium’s subsidization of EDA tools to commercialize their ideas more rapidly.
Big industry stakeholders bring significant IP to the table, but want to ensure competitors do not free ride off their contributions. To that end, they often call for multiple tiers of membership that match IP rights to contribution levels. Though big companies are more willing than start-ups to share background IP, they demand robust licensing frameworks to ensure their technology is not misused by competitors.
Academia differs from private sector members in that university IP often comes with limitations. Their background inventions are often funded by government grants that regulate licensing terms, end-uses, and ownership transfers. A consortium must prevent members from inadvertently violating the rules around any background IP, but caution is especially warranted for universities’ contributions.
At the time of this report’s writing, the White House has announced an interagency agreement that “outlines the goals and processes for determining the strategy and membership structure of the NSTC Consortium,” but the contents of the agreement are not yet public. As they move forward in this membership selection process, Natcast officials will have to carefully consider the IP interests of the members it admits. The consortium may need to subsidize startup and academia members who cannot contribute background IP as readily as large firms.
Setting an agenda
Research consortia can focus on basic research, applied research, prototyping, or scaling. More often, though, they adopt an agenda spanning the research stack.
Basic research pursues fundamental advancements in core scientific disciplines, like physics and chemistry. This usually calls for a public/open access model, where people in and out of the consortium can apply research results to starkly different fields. Often, only consortia with large government funding or broad memberships can afford to make their findings free.
Applied research leverages existing science to address immediate commercial needs. As a result, members worry about non-contributors free riding off the consortium’s work, and call for a shared-limited model. These models often involve nonexclusive royalty-free licenses (NERFs) granting consortium members free but limited use of jointly developed IP.
Prototyping and scaling take focus on how to manufacture and commercialize an innovation. Here, consortia help companies prepare their already well-developed ideas for production and commercialization, so there is no question of sharing this IP with competitors. Consortia engaging in this end of the stack must use exclusive models that compensate the consortium via revenue shares and IP royalties.
In consortia that research more than one piece of the technology stack, it becomes important to categorize technology properly. Whether a specific research project qualifies as basic research, applied research, prototyping, or scaling determines who has access to the resulting IP. The Department of Energy has faced challenges in the past where proprietary user-facility agreements prevented its laboratories from accessing information about industry partners’ research results. Though facility users had to report what patentable technologies resulted from their activities, they did not have to report these technologies’ commercial applications, which in turn limited the DOE’s ability to determine the technology readiness level (TRL) and ultimate value of its research products.
Having incomplete information about its facilities’ research products is not fatal for the DOE labs. Because they do not function as a research consortium, DOE labs are not at risk of improperly allocating IP rights if they misunderstand the use cases of clients’ IP. The NSTC, however, must ensure it retains insight into the commercial applications of its research results. If it fails to, it will not be able to properly categorize the TRL of the research it produces and so may improperly allocate IP rights to its members.
Geography
As responsible stewards of taxpayer dollars, Commerce officials are right to pursue efficiency while implementing the CHIPS Act. The Department noted in its September 2022 strategy paper that achieving its resilient chip supply chain goals “requires co-location of resources in particular geographic regions to achieve economies of scale and spillover benefits.” Officials need to be careful, however, that co-location for financial reasons does not relinquish control of the NSTC to the next door companies with whom it cooperates.
In theory, a program like the NSTC could be fully centralized, fully distributed, or follow a hybrid model. Most stakeholders suggest the latter because existing academic and corporate facilities already have parts of the infrastructure needed for the NSTC. In these models, there is a core NSTC facility, as well as several satellite “Centers of Excellence” (CoEs) serving specific functions.
Industry stakeholders, namely large semiconductor manufacturers, advocate a decentralized approach. One prominent response to a Commerce Department request for information on the NSTC said that a single NSTC location with full-flow capabilities is not necessary. Rather, the NSTC could function as a “distributed full flow” connecting nationwide hubs. Chipmakers clearly prefer decentralized hubs pursuing specific technology verticals because these hubs could advance their preexisting research agendas. Intel has proposed setting up an Advanced Packaging Lithography Center and assisting with an Advanced Packaging Manufacturing Center, both of which would operate as standalone physical facilities tied to the broader NSTC ecosystem. Micron has urged the NSTC to create a Memory Center of Excellence built adjacent to existing leading-edge facilities, namely Micron’s own in Boise, Idaho. The manufacturers’ philosophy is captured by TSMC’s position, which calls for the NSTC’s Centers of Excellence to feature both specific focus areas and economically self-sustainable business models. In other words, such a vision would empower CoEs to operate more or less independently of each other, the overall NSTC, and Washington.
On the other hand, academics, federal labs, and the most R&D-intensive semiconductor companies (namely, fabless design firms) advocate a more centralized version of the “hybrid” NSTC model. Evolving semiconductor technology and supply chains at a fundamental level requires early orchestration at the R&D stage, and these groups are concerned that siloed R&D at one stage of the technology “stack” could cause incompatibility with advancements further up or down. To that end, centralization advocates call for the NSTC to be led by a strong core with Centers of Excellence (CoEs) that play only a secondary role. Composed of early-stage research, equipment suppliers, chip customers (OEMs), or chip manufacturers, the CoEs would not pursue independent technology verticals, but rather research different stages of a centrally determined technology goal.
We support a hybrid model, leaning toward greater centralization of facilities in pursuit of a unified research agenda. Whether Congress ultimately decides to renew the NSTC’s funding after the five years of CHIPS Act support dry out may hinge on the consortium’s track record at moonshots. If it just becomes a subsidy for existing industry R&D plans, members of Congress may not view the NSTC as an improvement on dedicated CHIPS manufacturing subsidies. When debates about a “CHIPS Act Part II” commence around 2027, Congress may even choose to follow long-standing industry calls to subsidize R&D directly through tax credits, in lieu of extending an administratively complex consortium. However, if the NSTC leads to paradigm shifts in computing technology that benefit more than just the largest industry incumbents, it may become an American institution with staying power.
Funding trajectory
To understand how infrastructure and funding sources are interrelated, it helps to recall that Imec had a long path to its low level of government funding (17%). The consortium’s first year in 1984 posted 90% public funding, falling to 50% in 1992, and close to its present-day levels at 20% by 2004. Because a wide range of companies pay membership fees, no one firm commands its long-term research agenda.
To establish a centralized model and control over its long-term agenda, the NSTC should follow a path similar to Imec, as outlined in a MITRE Engenuity February 2023 paper:
In the first five years, the NSTC should build out its infrastructure primarily with public CHIPS Act funds, setting the consortium’s foundation without controlling pressure by any single company. The independence brought by funding infrastructure investments with public dollars would reduce the NSTC’s need to make large concessions to companies next to whose facilities it may need to build annexes. Such concessions could include requiring that the annex pursue existing research priorities of the host company or even committing fab time to some of the host company’s individual competitive research.
In the second five years, the NSTC should rely more heavily on participation fees for joint projects, but public dollars should continue funding significant investments in infrastructure to ensure new facility plans do not only serve narrow private interests.
Finally, with most infrastructure having been built and its research agenda largely set, the NSTC can confidently engage in more direct fee-for-service projects with companies without fear that it will become over-reliant on a small number of players.
Conclusion: What the semiconductor industry really needs
As the semiconductor industry gets ever more complex, it needs greater cross-industry collaboration. Throughout chipmaking’s history, public-private partnerships have facilitated cooperation between siloed competitors, but the industry’s current research and investment agendas feature market failures that existing consortia cannot solve.
The chip industry was born in America, and a sufficiently ambitious NSTC can ensure the next generation of computing technology is continued here. The consortium must help players of different sizes across the chip industry address important shortfalls in their research agendas: startups need commercial-grade facilities to test their designs’ production viability, incumbents and newcomers both need a partner committed to developing new materials and process chemicals, and large siloed firms need forums for cooperation on cross-sectoral missions.
Similarly, the NSTC must fill gaps in the industry’s investment agenda. Mid-stage startups need targeted support from technically informed investors to survive until commercialization. Startups with offerings outside the latest trends need a sharp-eyed investor thinking about the industry’s long-term needs. And other investors need a player with both technical knowledge and financial muscle to organize funding syndicates for promising upstarts.
If the NSTC’s ambitious research and investment agendas complement those of private industry, the once-in-a-generation consortium can make a strong argument to Congress for continued funding in its later years. Legislators must remain convinced that the consortium thinks broadly about American innovation and can produce moonshots that direct industry subsidies could not. With Natcast leadership appointed and ready to build the NSTC from the ground up, we hope these recommendations help the U.S. “drive the pace of innovation, set standards, and re-establish global leadership in semiconductor design and manufacturing.”
Appendix: IP-sharing models
Public-private partnerships around the world feature different funding sources, memberships, and research agendas, offering fascinating illustrations of IP sharing in different settings. As Natcast leadership becomes clearer on the proportion of the center’s annual budget that comes from the government, its membership, and its research agenda, these precedents offer guidance on which IP sharing model would be most sustainable for the NSTC.
Imec
Although Belgium’s Imec also only receives a small share – 17% – of its funding from the Flemish government, other structural characteristics allow it to operate under a more open shared limited model.
On the funding side, readers will recall that consortia receiving limited funding from their governments have two options: seek IP revenue or lean on membership fees. Imec does the latter, relying on fees to fund its facilities. As a result, Imec neither requires members to share their background IP nor takes sole ownership of the center’s IP.
A diverse membership further encourages Imec’s shared limited model. Called the Imec Industrial Affiliation Program (IIAP), research partners in specific technical areas establish shared limited ecosystems where members receive rights to foreground IP proportionate to the background IP they contribute. This allows start-ups to participate despite having less IP to offer than established firms, whereas they would be repelled by the rigidity of Germany’s Fraunhofer or China’s NHSTTC.
Beyond its diverse membership, Imec’s wide research agenda requires different IP approaches depending on the stage of research. Early-stage research is less sensitive, so Imec shares these results with all fee-paying members. However, as technology climbs up the stack toward applied research, access is tightened to only members directly collaborating on the project. Imec rarely offers exclusive licenses as those would shortchange fee-paying members.
ITRI
Receiving 65% of its nearly $700 million annual budget from the Taiwanese government, ITRI has a public orientation similar to Japan’s AIST, but it also has exclusive arrangements for later-stage R&D.
As most of its R&D projects use funds from the Ministry of Economic Affairs, ITRI’s IP model is obliged by Taiwan’s Basic Law of Science and Technology to be fair, open-access, and non-exclusive. Like Germany’s Fraunhofer and China’s NHSTTC, ITRI itself owns the IP it develops. In contrast to those exclusive models, however, partners collaborating with ITRI on basic research projects are not expected to commit significant background IP or fees, and in return for participation they receive shared limited use of the R&D results.
In addition to its government-sponsored basic research work, ITRI also pursues later-stage projects and commissioned work requiring exclusive IP models. When companies commission ITRI to solve specific problems, the consortium must offer exclusive licenses giving clients full competitive advantage over the technology they purchased.
Leti
Public announcements by Leti often mention that subsidies from the French government account for only 20% of its annual budget of 330 million euros. It is true that, over the past decade, direct public funding has only made up about a third of Leti’s budget —with most of these public funds allocated to academic research and education. However, another third of its budget comes from public funding through research contracts, and only the final third is purely funded by industry.
This segmentation of public funding allows the French state to support its industrial champions without violating EU regulations. CEA, Leti’s governing body, remains the owner of the results obtained by Leti researchers; it also retains the “industrial building blocks” (basic patents) of bilateral projects. These “industrial building blocks” not only help disseminate know-how to startups but, as a former director of CEA’s investment fund and head of Leti’s microelectronics program noted, “Leti’s objective is not to do research for research’s sake but to help our industrial champions grow.” To that end, Leti not only keeps its patents in France, but also grants preferential licensing terms to French and European companies over their non-European counterparts. As a result, Leti’s IP policy bolsters France’s technological sovereignty by preventing innovations – and innovators – from leaking out of the country.
Leti’s private sector partners certainly also influence its program since they contribute a third of its budget. However, the levers of the French state –Leti’s public contracts, as well as other administrative checks – maintain public influence capable of setting the laboratory’s research agenda.
AIST
Receiving nearly its entire budget from the government and working with a broad range of research partners, Japan’s AIST functions most closely to a public research organization.
About 75% of AIST’s over $700 million annual budget comes from government funding. Specifically, a large share of these funds are specifically commissioned to explore basic science. The results of these projects are often public, not needing a license, and Japan’s Science and Technology Agency has underscored the importance of open access to research in the information and communication technology (ICT) sector.
Beyond its public research, AIST does conduct joint research work with universities and companies partners, calling for some shared limited IP arrangements. In these partnerships, AIST follows a tack similar to that of Imec, in welcoming partners to leverage background IP in return for joint ownership of foreground IP that can be non-exclusively licensed for limited purposes.